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SpecialReport

New 1.1-GHz G3 Chip The next iBook CPU?

Wednesday, July 2, 2003

By Applelinks Contributing Editor Charles W. Moore

The PPC 970/G5 isn’t the only news in the Power PC CPU orbit these days. There’s lots of life in the old 32-bit G3 yet. Yesterday, IBM announced its latest G3 750 family chip - the 750GX, codenamed “Gobi” continuing the “desert” theme. The 800 MHz and 900 MHz G3 750FX chips used in the current iBooks are codenamed “Sahara.”

IBM engineer Mark Schaffer describes the 750GX or “Gobi,” as “offering world-class performance at very low power levels utilizing its leading-edge process technologies to meet these requirements.”

Sampling for this new processor is scheduled for July 2003 with production targeted for December 2003. It would seem like a logical candidate to power the iBook, but Apple has not tipped its hand on what’s in store in that regard. There continues to be speculation about the iBook going G4, but the G3 has formidable advantages in terms of low power consumption and relatively low heat generation that make it a more ideal CPU for portable computers than the G4, at least for users who aren’t heavily into running Altivec optimized software like Adobe PhotoShop. With non-optimized applications (ie: most applications), there will be little difference in performance whether you’re using a G3 or a G4.

Manufactured in IBM’s advanced 0.13-micron copper process with Silicon-on-Insulator technology that are used in the current 750FX “Sahara” G3s in which it is based, the 750GX will be offered at frequencies up to 1.1 GHz. The 750GX expands the capabilities of the IBM PowerPC 7xx processor family to support more performance-demanding and power-sensitive applications.

The 750GX includes 1 MB of internal L2 cache, 4-way set-associative, running at core frequency with cache locking by way, additional L1 and L2 cache buffers allowing pipelining of up to four data cache miss operations, and the capability for up to 200-MHz operation of the 60x system bus interface with additional bus pipelining.

According to Mark Schaffer:

“The integrated 1 MB of L2 cache operates at the processor’s core frequency, providing minimal latency for instruction fetch operations and data load operations that hit in the L2 cache. The larger size of the internal L2, twice that available on the 750FX, provides more on-chip memory storage for performance-critical application code and data, and may provide a significant performance improvement, due to the size alone. In addition, the L1 data cache path to the Bus Interface Unit (BIU) and the L2 cache reload path to the L1 data cache are 256 bits wide. With these wide data paths, cache line data bursts can be read from or written to the cache array in a single cycle, reducing cache contention between the BIU and the load-store unit. With 1 MB of low-latency integrated L2 cache, the 750GX is designed to reduce the overall system cost and power by eliminating the need for external L3 memory arrays and lowering the board space requirements....

“Cache line miss buffers have been added between the L1 data cache and the L2 cache as well as between the L2 cache and the BIU, allowing for up to four-deep pipelining of L1 cache miss transactions. The four transactions can be either four data cache miss transactions or a combination of three data cache miss transactions and one instruction cache miss transaction. In addition, the BIU in the 750GX has been enhanced to provide support for the deeper cache miss pipelining and can now pipeline up to five load/store bus transactions, four from the L2 cache miss queues and one from the L2 cache cast-out buffer. With this enhanced pipelining from the L1 cache through the L2 cache and out to the bus interface unit, the 750GX is designed to improve the overall system performance and bus utilization, allowing applications to take advantage of the higher processing capability that the 750GX processor offers.

“The L2 cache has also been enhanced to provide an instruction-side-only mode, which allows only the L1 instruction cache transactions to be allocated within the L2 cache. Data-side transactions are not allocated in the L2 and are read from and written to memory directly from the L1 data cache. This mode is useful for applications that do not benefit from the data-side cache and improves the performance of the L2 cache for the instruction side by not replacing L2 cache lines due to data load and store operations.”

Schaffer also says that the 750GX is fully user-code-compatible with the other members of the IBM 7xx processor family, providing an easy software-migration path to higher processing performance, which would make it and easy speed bump for 750FX machines like the iBook, and also a candidate for processor upgrade products like PowerLogix’s PowerBook Pismo G3 upgrades, currently offered at 800 MHz and 900 MHz with 750FX chips. The 750GX is pin- and voltage-compatible with the 750FX, eliminating the need for a board redesign to achieve higher performance and allowing for the use of a common board design. However, the 750GX is physically larger than the 750FX: 51.9mm square compared to 36.6mm square, and draws more power (8.0 W at 1 GHz vs. 5.4 W with the 750FX at 800 MHz, but that’s still only a bit more than half a 1 GHz G4’s 15 W draw).

The IBM 32 bit PowerPC 7xx processor family

750CXe: 400 - 600 MHz /256 KB L2 cache/6.0 W @ 600 MHz

750FX: 600 - 900 MHz /512 KB internal cache/ 5.4 W @ 800 MHz

750GX: 733 MHz - 1.1 GHz /1 MB cache/ 8.0 W @ 1 GHz

An even faster IBM 750 series chip of 1.4 GHz and up is reportedly in the works, codenamed “Mojave,” and rumored to incorporate a vector processing engine (Altivec-style). Since the most substantial difference between a G3 and a G4 is the vector engine, it is probable that iBooks (or even PowerBooks?) with the Mohave chip inside would be marketed as G4s, although that’s just speculation at this point

For more information on the 750GX, visit here.


Charles W. Moore

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